PCI Express 4.0: What it is and why it’s important

Nearly two years after its formal introduction, PCI Express 4.0
is finally here. The specification promises higher speeds than the
previous generation for internal storage, graphics cards, and more.
What is PCI Express 4.0 exactly and why does it matter to you?
Let’s take a look without getting too crazy technical.

Peripheral Component Connect (PCI)

To understand PCI Express, we need to start with its
predecessor. Intel created the original PCI computer bus in 1992.
It replaced the EISA and MCA expansion buses in servers, and the
VESA Local Bus in mainstream PCs. A bus is a hard-wired
“highway” on a motherboard linking components in a computer.
There are many buses serving different purposes, like the Universal
Serial Bus supporting printers, mice, and keyboards.

PCI relies on parallel transmission that sends and receives data
simultaneously across multiple lines. In contrast, serial
transmission sends data just one bit at a time. If both move data
at the same speed, the parallel transmission appears “faster”
due to the transmitted data amount.

PCI relies on parallel transmission that sends and receives data
simultaneously across multiple lines.

The problem with a parallel design is that it requires all lines
to be synchronized, limiting data rates and frequency. Moreover,
signals from bad wiring can leak and interfere with neighboring
wires, creating “crosstalk” that slows data. To prevent
“crosstalk,” PCI lines can’t extend above a specific length,
which is typically shorter than serial connections.

Another issue with PCI in general is that it uses a shared
architecture. The PCI host and all connected PCI-based devices
share the same address, control, and data lines. This presents a
problem, as the bus clock throttles down to support the slowest
connected device on the bus. Even more, all the wiring needed to
support parallel transfers make PCI a pricier design for
manufacturers.

Finally, PCI supports up to five external devices, two of which
can be swapped out for fixed internal components. The PCI bus has a
fixed 64-bit width, limiting the data amount passing through the
bus each second:

Speed Width Clock PCI version
133 MB/s 32-bit 33 MHz 1.0
266 MB/s 64-bit 33 MHz 1.0
266 MB/s 32-bit 66 MHz 2.1
533 MB/s 64-bit 66 MHz 2.1

Peripheral Component Connect Express (PCI Express, PCI-E,
PCIe)

In 2003, Intel teamed up with Dell, IBM, and HP to create
Peripheral Component Interconnect Express. These four companies are
part of the Peripheral Component Interconnect Special Interest
Group (PCI-SIG), a consortium
originally formed in 1992 to govern the PCI specification. With
processors and graphics cards growing exponentially faster, the
consortium saw the need for a new system.

PCI Express is different than PCI in that it ditches parallel
communication and uses dedicated serial connections instead. One
serial connection with a higher clock can match the speed of
multiple parallel lines moving the same load. As previously stated,
a serial bus costs less to manufacture.

PCI Express resembles an on-board network. It provides private
point-to-point access to each connected device and a switch
managing these connections. Supported devices include internal
storage, graphics cards, and networking components.

A single PCI Express connection contains up to 32 “lanes,”
depending on the device slot. Each lane includes two pairs of
wires: One pair that sends data and one pair that receives data.
For example, a PCI Express connection with only one lane features
four wires.

Take a look:

Type Serial connection(s) / lane(s) Wires Bits per cycle in each direction
x1 1 4 1
x2 2 8 2
x4 4 16 4
x12 12 48 12
x16 16 64 16
x32 32 128 32

The initial PCI Express specification enabled a one-way speed of
250MB per second across a single (x1) lane. PCI Express 2.0 doubled
that speed to 500MB per second. Version 3.0 introduced a new
encoding method that nearly doubled the per-lane speed again.

Typically, with each new revision, the PCI-SIG announces higher
speeds in “gigatransfers” (GT). This term describes a
measurement of data in gigabits transferred every second. But due
to how the serial bus encodes data, this hard limit will never be
fully utilized.

Gigatransfers describes a measurement of data in gigabits
transferred every second in each direction simultaneously.

Why? Because pictures, documents, and files
must be broken down (encoded) into binary data for
transmission over wires. This data is then reconstructed (decoded)
on the receiving end. Part of this binary data is the required
encoding/decoding information.

For instance, PCIe 1.0 and 2.0 uses 8b/10b encoding, meaning 10
bits of data are moved for every 8 bits. That encoding formula
changed to 128b/130b in the PCIe 3.0 specification, requiring two
extra bits for every 128 bits. In other words, a lot more data
passes across the connection.

Here’s a chart to show gigatransfers and their translated
one-way speeds.

Version Gigatransfers per second One lane (x1) Sixteen lanes (x16)
1.x 2.5 250MB/s (2Gbps) 4GB/s (32Gbps)
2.x 5 500MB/s (4Gbps) 8GB/s (64Gbps)
3.x 8 985MB/s (7.88Gbps) 15.75GB/s (126Gbps)
4.x 16 1.969GB/s (15.75Gbps) 31.51GB/s (252Gbps)
5.x 32 3.938GB/s (31.5Gbps) 63.01GB/s (504Gbps)

As an example, the chart above shows lanes moving data in one
direction. For PCI Express 1.0, a single lane moves two gigabits
(2Gb) of unencoded data each second. That amount increases to 2.5Gb
of encoded data due to the 8b/10b encoding process.

After PCI Express 1.0, the 2.0 specification arrived in 2007
followed by the current standard, PCI Express 3.0, in 2010. The
consortium didn’t finish the PCI Express 4.0 specification until
2017. That timeline leads us to the current big news issued during
Computex in June.

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The arrival of PCI Express 4.0

Officially launched
in October 2017
, PCI Express 4.0 brings the gigatransfers up to
16 per second, or 15.75Gb of unencoded data per second. In the
seven-year gap between 3.0 and 4.0, we’ve seen huge growth in M.2
SSDs that utilize PCI Express connectivity. Intel’s Thunderbolt 3
port promises up to 40Gb per second transfer speeds thanks to PCI
Express lanes.

As processors climb in core count, and GPUs juggle larger
textures, all this big data needs a proper transport. It needs a
fast backbone in place to prevent system latency. PCI Express 4.0
ushers in faster speeds and larger data chunks to handle new
powerful components that demand super-fast connections.

What graphics cards support PCI Express 4.0?

Computex 2019 AMD keynote

AMD will launch the Radeon
RX 5700 “Navi” series in July
. Based on 7nm process
technology, this GPU family features a new from-scratch Radeon DNA
(aka RDNA) graphics core architecture. RDNA supports PCI Express
4.0 and GDDR6 video memory. AMD CEO Lisa Su said RDNA will power
gaming for the next ten years.  GCN will still be around for
Vega-based products and high workload applications.

At the time of this publication, we didn’t know the actual
models planned for AMD’s RX 5700 family. AMD’s Computex keynote
provided a glimpse into their performance through a benchmark of
Strange Brigade. The game ran on Nvidia’s RTX 2070 and an
unreleased Radeon RX 5700 card. The result: AMD’s card saw
“roughly” 10 percent better performance than the RTX 2070.

Meanwhile, AMD’s Radeon Instinct
M150
and
MI60
compute cards for deep learning and high performance
computing support PCI Express 4.0.
Launched in November 2018
, they’re based on the “world’s
first” 7nm GPU, the Vega 20.

Related: Google
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What CPUs support PCI Express 4.0?

Computex 2019 AMD keynote

AMD’s third-generation Ryzen
3000 Series desktop CPU family supports PCI Express 4.0
. Five
desktop parts will be available on July 7:

  Cores / Threads PCIe 4.0 lanes (CPU) PCIe 4.0 lanes (chipset) Price
Ryzen 9 3900X 12 / 24 24 16 $499
Ryzen 7 3800X 8 / 16 24 16 $399
Ryzen 7 3700X 8 / 16 24 16 $329
Ryzen 5 3600X 6 / 12 24 16 $249
Ryzen 5 3600X 6 / 12 24 16 $199

Note that AMD advertises 40 PCI Express 4.0 lanes with its new
Ryzen desktop CPUs, which is a shared number. The chipset provides
16 PCI Express lanes while the CPU provides another 24:

  • 16 = GPU
  • 4 = Storage
  • 4 = Chipset

One of the big selling points with Ryzen and the AM4 socket is
backwards compatibility. For example, you don’t need a new
motherboard when upgrading from a Ryzen 1000 to a Ryzen 3000 chip.
Technically, if you wanted the latest features, swapping
motherboards is a good idea. But if you simply want a newer
processor, a motherboard replacement isn’t necessary.

But to get full PCI Express 4.0 support, you’ll need a Ryzen
3000 processor and a X570-based motherboard. That wasn’t the case
earlier this year, as manufacturers enabled PCI Express 4.0 on
older motherboards through a BIOS update. AMD backtracked on this
decision, however, and now blocks PCI Express 4.0 updates on
everything prior to X570-based motherboards.

AMD now blocks PCI Express 4.0 updates on everything prior
X570-based motherboards.

The reason?
Signal integrity
. PCI Express 4.0 demands wider spacing than
the PCI Express 3.0 layouts on current motherboards. The new spec
also requires transmit and receive traces on multiple layers.
Traces are those small copper or aluminum lies running across the
motherboard.

“There’s no guarantee that older motherboards can reliably
run the more stringent signaling requirements of Gen4, and we
simply cannot have a mix of ‘yes, no, maybe’ in the market for
all the older motherboards,”
says senior technical marketing manager Robert Hallock
. “The
potential for confusion is too high.”

Due to the hardware constraints, AMD’s advertised backward
compatibility with Ryzen now doesn’t include PCI Express 4.0.

PCI Express 5.0 approval

Look around the internet and you’ll see reports that PCI
Express 5.0 is already here. The
PCI-SIG announced the specifications’ availability
just
before Computex in June,
minimalizing the PCI Express 4.0 aspect of AMD’s big reveal.
What’s the point of PCI Express 4.0 with a newer specification on
the horizon, right?

Technically, PCI Express 5.0 isn’t here for
you, the end-user. It’s here for manufacturers.
Twenty-one months will have passed between the 4.0 spec
availability and the first real product utilizing that spec. Using
the same pattern, we likely won’t see hardware based on PCI
Express 5.0 until February 2022. If we’re lucky, we’ll see
product reveals during the CES 2022 technology convention in Las
Vegas.

PCI Express 5.0 will support up to 32 gigatransfers per second.
That’s 31.5Gb of unencoded data each second one way per lane. For
example, if an x1 graphics card is sending and receiving data
simultaneously, that’s around 8GB per second combined. An x16
graphics card could see data transfers of up to 128GB per
second.

Given PCI Express 5.0 version 1.0 is now available to
manufacturers, we have no information regarding upcoming products.
AMD, Epson, Intel, Nvidia, and Silicon Labs are just a few
companies already pledging allegiance to the new specification.

Conclusion

PCI Express 4.0 is here in physical form to support faster
processors, graphics cards, storage devices, and more. The rollout
may be slow at first with AMD’s Ryzen 3000 and Radeon RX 5700
products leading the pack. We definitely have plenty of time for
the PCI Express 4.0 market to grow before version 5.0 actually
arrives.

But as seen with AMD, adding support for PCI Express 4.0 to
older hardware may be problematic. BIOS-based upgrades will depend
on manufacturers and their motherboard designs. However, as noted,
AMD will not enable PCI Express 4.0 on anything older than
X570-based motherboards.

Currently we don’t know Intel’s plans for PCI Express 4.0.
Its upcoming 10th-generation “Ice Lake” processors, however,
will not support the new specification when they arrive during the
2019 holiday season.

If you’re looking for a new laptop, here are a few “best”
guides (and they don’t have PCI Express 4.0):

Source: FS – Android
PCI Express 4.0: What it is and why it’s important